`include "ascon_define.v"

module `ANY_CYC
    #(
     parameter DAT_W                             = 1,
     parameter CYC_N                             = 1
     )
     (
     input                                       clk_i,
     input                                       rst_n_i,
     input                                       en_i,
     input                           [DAT_W-1:0] dat_d_i,

     output                          [DAT_W-1:0] dat_q_o
     );


localparam CNT_W                                 = $clog2(CYC_N);

reg                                  [DAT_W-1:0] d_rag [CYC_N-1:0];

assign dat_q_o          = d_rag[CYC_N-1];

genvar index;

generate

for (index = 0 ; index < CYC_N;index = index + 1 )
begin : D_RAG_LOOP
if (index == 0)

always @(posedge clk_i or negedge rst_n_i)
begin : D_RAG_PROG
  if (rst_n_i == 1'b0)
    d_rag[index]        <= {DAT_W{1'b0}};
  else if(en_i == 1'b1)
    d_rag[index]        <= dat_d_i;
  else
    d_rag[index]        <= d_rag[index];
end

else

always @(posedge clk_i or negedge rst_n_i)
begin : D_RAG_PROG
  if (rst_n_i == 1'b0)
    d_rag[index]        <= {DAT_W{1'b0}};
  else if(en_i == 1'b1)
    d_rag[index]        <= d_rag[index-1];
  else
    d_rag[index]        <= d_rag[index];
end

end

endgenerate

endmodule